ShareFloat CIM: A Compute-In-Memory Architecture with Floating-Point Multiply-and-Accumulate Operations
Author:
Affiliation:
1. Southeast University,Nanjing,China
Funder
National Natural Science Foundation of China
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9937201/9937203/09937242.pdf?arnumber=9937242
Reference14 articles.
1. Low Bit-Width Convolutional Neural Network on RRAM
2. Analog Deep Neural Network Based on NOR Flash Computing Array for High Speed/Energy Efficiency Computation
3. A 40nm 1Mb 35.6 TOPS/W MLC NOR-Flash Based Computation-in-Memory Structure for Machine Learning
4. 15.2 A 2.75-to-75.9TOPS/W Computing-in-Memory NN Processor Supporting Set-Associate Block-Wise Zero Skipping and Ping-Pong CIM with Simultaneous Computation and Weight Updating;yue;In 2021 IEEE International Solid-State Circuits Conference (ISSCC),2021
5. C3SRAM: An In-Memory-Computing SRAM Macro Based on Robust Capacitive Coupling Computing Mechanism
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1. A 28-nm 64-kb 31.6-TFLOPS/W Digital-Domain Floating-Point-Computing-Unit and Double-Bit 6T-SRAM Computing-in-Memory Macro for Floating-Point CNNs;IEEE Journal of Solid-State Circuits;2024-09
2. Toggle Rate Aware Quantization Model Based on Digital Floating-Point Computing-In-Memory Architecture;IEEE Transactions on Circuits and Systems II: Express Briefs;2024-06
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