Fabrication of self-aligned 90-nm fully depleted SOI CMOS SLOTFETs-Reference-Cited by-同舟云学术

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Fabrication of self-aligned 90-nm fully depleted SOI CMOS SLOTFETs

Published:2001-07 Issue:7 Volume:22 Page:345-347
ISSN:0741-3106
Container-title:IEEE Electron Device Letters
language:
Short-container-title:IEEE Electron Device Lett.

Author:

Chen C.K.,Chen C.L.,Gouker P.W.,Wyatt P.W.,Yost D.R.,Burns J.A.,Suntharalingam V.,Fritze M.,Keast L.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx5/55/20129/00930686.pdf?arnumber=930686

Cited by 6 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A novel nanoscale MOSFET with modified buried layer for improving of AC performance and self-heating effect;Materials Science in Semiconductor Processing;2012-08

2. Fabrication of Highly Scaled Silicon Nanowire Gate-All-Around Metal–Oxide–Semiconductor Field Effect Transistors by Using Self-Aligned Local-Channel V-gate by Optical Lithography Process;Japanese Journal of Applied Physics;2010-08-20

3. Fabrication and characterization of a 0.14 μm CMOS device using ATHENA and ATLAS simulators;Semiconductor physics, quantum electronics and optoelectronics;2006-04-30

4. Fabrication of ultra-thin-film SOI transistors using the recessed channel concept;Microelectronic Engineering;2005-03

5. Simulation of the Esaki-tunneling FET;Solid-State Electronics;2003-07

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