A Digital LDO in 22nm CMOS with a 4b Self-triggered Binary Search Windowed Flash ADC Featuring Automatic Analog Layout Generator Framework-Reference-Cited by-同舟云学术

A Digital LDO in 22nm CMOS with a 4b Self-triggered Binary Search Windowed Flash ADC Featuring Automatic Analog Layout Generator Framework

Published:2022-11-06 Issue: Volume: Page:
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Container-title:2022 IEEE Asian Solid-State Circuits Conference (A-SSCC)
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Author:

Liu Xiaosen¹,Yaldiz Soner²,Mukherjee Parijat²,Burns Steven²,Krishnamurthy Harish²,Ravichandran Krishnan²,Ahmed Zakir²,Desai Nachiket²,Butzen Nicolas²,Tschanz James²,De Vivek²

Affiliation:

1. Tsinghua University,School of Integrated Circuits,Beijing,China

2. Intel Corporation, Intel Labs,OR,U.S.A

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9980472/9980536/09980543.pdf?arnumber=9980543

Reference6 articles.

1. 22.6 A 2.2GS/s 7b 27.4mW time-based folding-flash ADC with resistively averaged voltage-to-time amplifiers

2. MAGICAL: An Open- Source Fully Automated Analog IC Layout System from Netlist to GDSII

3. A 2.2mW 5b 1.75GS/s Folding Flash ADC in 90nm Digital CMOS

4. A 65 nm CMOS 7b 2 GS/s 20.7 mW Flash ADC With Cascaded Latch Interpolation

5. Invited: open-source EDA tools and IP, a view from the trenches;alon;DAC,2019

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