Analog Layout Automation On Advanced Process Technologies
Author:
Affiliation:
1. Intel, Hillsboro, OR, USA
Funder
DARPA
Publisher
ACM
Link
https://dl.acm.org/doi/pdf/10.1145/3569052.3578915
Reference5 articles.
1. A. L. S. Loke et. al "Nanoscale CMOS Implications on Analog/Mixed-Signal Design " 2019 IEEE CICC 2019. A. L. S. Loke et. al "Nanoscale CMOS Implications on Analog/Mixed-Signal Design " 2019 IEEE CICC 2019.
2. H. E. Graeb "Analog Layout Synthesis A Survey of Topological Approaches" Springer 2011. H. E. Graeb "Analog Layout Synthesis A Survey of Topological Approaches" Springer 2011.
3. H. Ren and J. Hu , " Machine Learning Applications in Electronic Design Automation ", Spring Cham , 2023 . H. Ren and J. Hu, "Machine Learning Applications in Electronic Design Automation", Spring Cham, 2023.
4. T. Dhar etal "ALIGN: A System for Automating Analog Layout " in 2021 IEEE Design & Test. T. Dhar et al. "ALIGN: A System for Automating Analog Layout " in 2021 IEEE Design & Test.
5. X. Liu et. al. "A Digital LDO in 22nm CMOS with a 4b Self-triggered Binary Search Windowed Flash ADC Featuring Automatic Analog Layout Generator Framework " 2022 IEEE A-SSCC. X. Liu et. al. "A Digital LDO in 22nm CMOS with a 4b Self-triggered Binary Search Windowed Flash ADC Featuring Automatic Analog Layout Generator Framework " 2022 IEEE A-SSCC.
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