A 65 nm CMOS 7b 2 GS/s 20.7 mW Flash ADC With Cascaded Latch Interpolation-Reference-Cited by-同舟云学术

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A 65 nm CMOS 7b 2 GS/s 20.7 mW Flash ADC With Cascaded Latch Interpolation

Published:2015-10 Issue:10 Volume:50 Page:2319-2330
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Kim Jong-In,Oh Dong-Ryeol,Jo Dong-Shin,Sung Ba-Ro-Saim,Ryu Seung-Tak

Funder

MSIP (Ministry of Science, ICT & Future Planning), Korea, in the ICT R&D Program 2015

Institute for Information & Communications Technology promotion (IITP)

IDEC of KAIST

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/7279217/07206614.pdf?arnumber=7206614

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3. An artificial intelligence‐based 4‐to‐10‐bit variable resolution Flash ADC with 3.6 to 1.04 GS/s sampling rate;International Journal of Circuit Theory and Applications;2024-01-23

4. ConvFIFO: A Crossbar Memory PIM Architecture for ConvNets Featuring First-In-First-Out Dataflow;2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC);2024-01-22

5. A 0.004-mm² 3.65-mW 7-Bit 2-GS/s Single-Channel GRO-Based Time-Domain ADC Incorporating Dead-Zone Elimination and On-Chip Folding-Offset Calibration in 28-nm CMOS;IEEE Journal of Solid-State Circuits;2023-11

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