A 0.004-mm<sup>2</sup> 3.65-mW 7-Bit 2-GS/s Single-Channel GRO-Based Time-Domain ADC Incorporating Dead-Zone Elimination and On-Chip Folding-Offset Calibration in 28-nm CMOS-Reference-Cited by-同舟云学术

A 0.004-mm² 3.65-mW 7-Bit 2-GS/s Single-Channel GRO-Based Time-Domain ADC Incorporating Dead-Zone Elimination and On-Chip Folding-Offset Calibration in 28-nm CMOS

Published:2023-11 Issue:11 Volume:58 Page:3179-3193
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Zhang Chenghao¹^ORCID,Wei Jiangbo¹^ORCID,Chen Yong²^ORCID,Liu Maliang¹^ORCID,Yang Yintang¹^ORCID

Affiliation:

1. School of Microelectronics, Xidian University, Xi’an, China

2. State Key Laboratory of Analog and Mixed-Signal VLSI and IME/ECE-FST, University of Macau, Macau, China

Funder

Macau SAR

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/10292770/10153544.pdf?arnumber=10153544

Reference25 articles.

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3. A 15.1-mW 6-GS/s 6-bit Flash ADC with Selectively Activated 8× Time-Domain Interpolation

4. A 2.2 GS/s 7 b 27.4 mW time-based folding-flash ADC with resistively averaged voltage-to-time amplifiers;miyahara;IEEE ISSCC Dig Tech Papers,2014

5. A 7.8-mW 5-b 5-GS/s Dual-Edges-Triggered Time-Based Flash ADC

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