A Self-Clocked TDC-Based Unified Clock and Voltage Regulator with Replica Frequency-Locked Loop and Hysteresis Switching in 65nm CMOS
Author:
Affiliation:
1. The Hong Kong University of Science and Technology
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9980472/9980536/09980639.pdf?arnumber=9980639
Reference8 articles.
1. Time-Based Digital LDO Regulator with Fractionally Controlled Power Transistor Strength and Fast Transient Response;kang;ASSCC,2019
2. A 0.5-to-1.2V, 310nA Quiescent Current, 3fs-FoM Time-Domain Output-Capacitorless LDO with Propagation-Delay-Triggered Edge Detector
3. Postsilicon Voltage Guard-Band Reduction in a 22 nm Graphics Execution Core Using Adaptive Voltage Scaling and Dynamic Power Gating
4. A synthesizable time-based LDO using digital standard cells and analog pass transistor
5. UVFR: A Unified Voltage and Frequency Regulator with 500MHz/0.84V to 100KHz/0.27V operating range, 99.4% current efficiency and 27% supply guardband reduction
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1. A Dual-Loop LDO with Voltage-Controlled Oscillator Based Control;2024 IEEE 7th Advanced Information Technology, Electronic and Automation Control Conference (IAEAC);2024-03-15
2. A Fully Integrated Digital LDO With Adaptive Sampling and Statistical Comparator Selection;IEEE Solid-State Circuits Letters;2024
3. An Adaptive-Sampling Digital LDO with Statistical Comparator Selection Achieving 99.99% Maximum Current Efficiency and 0.25ps FoM in 65nm;2023 IEEE Asian Solid-State Circuits Conference (A-SSCC);2023-11-05
4. A Self-Clocked and Variation-Tolerant Unified Voltage-and-Frequency Regulator for In-Order Executed Digital Loads;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-11
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