Postsilicon Voltage Guard-Band Reduction in a 22 nm Graphics Execution Core Using Adaptive Voltage Scaling and Dynamic Power Gating-Reference-Cited by-同舟云学术

Postsilicon Voltage Guard-Band Reduction in a 22 nm Graphics Execution Core Using Adaptive Voltage Scaling and Dynamic Power Gating

Published:2017-01 Issue:1 Volume:52 Page:50-63
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Cho Minki^ORCID,Kim Stephen T.,Tokunaga Carlos,Augustine Charles,Kulkarni Jaydeep P.,Ravichandran Krishnan,Tschanz James W.,Khellah Muhammad M.,De Vivek

Funder

U.S. Government (DARPA)

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/7811159/07564406.pdf?arnumber=7564406

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