MBIST-based Trim-Search Test Time Reduction for STT-MRAM
Author:
Affiliation:
1. Karlsruhe Institute of Technology (KIT),Department of Computer Science,Karlsruhe,Germany
2. Siemens Digital Industries Software,Wilsonville,USA
Funder
Siemens
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9793839/9794139/09794178.pdf?arnumber=9794178
Reference23 articles.
1. Analysis of Defects and Variations in Embedded Spin Transfer Torque (STT) MRAM Arrays
2. Design of Defect and Fault-Tolerant Nonvolatile Spintronic Flip-Flops
3. Signal-Margin-Screening for Multi-Mb MRAM
4. A fully-functional 90nm 8Mb STT MRAM demonstrator featuring trimmed, reference cell-based sensing
5. Embedded MRAM Macro for eFlash Replacement
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1. Parallel-Check Trimming Test Approach for Selecting the Reference Resistance of STT-MRAMs;2024 IEEE European Test Symposium (ETS);2024-05-20
2. Design-for-Test for Intermittent Faults in STT-MRAMs;2024 IEEE European Test Symposium (ETS);2024-05-20
3. Multi-Level Reference for Test Coverage Enhancement of Resistive-Based NVM;2024 IEEE 42nd VLSI Test Symposium (VTS);2024-04-22
4. A Dynamic Testing Scheme for Resistive-Based Computation-In-Memory Architectures;2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC);2024-01-22
5. Smart Hammering: A practical method of pinhole detection in MRAM memories;2023 Design, Automation & Test in Europe Conference & Exhibition (DATE);2023-04
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