Multi-Level Reference for Test Coverage Enhancement of Resistive-Based NVM
Author:
Affiliation:
1. Karlsruhe Institute of Technology (KIT),Department of Computer Science,Karlsruhe,Germany
2. Tessent, Siemens Digital Industries Software,Wilsonville,OR,USA
3. Tessent, Siemens Digital Industries Software,Orlando,FL,USA
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10538470/10538498/10538585.pdf?arnumber=10538585
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1. JEDEC-Qualified Highly Reliable 22nm FD-SOI Embedded MRAM For Low-Power Industrial-Grade, and Extended Performance Towards Automotive-Grade-1 Applications
2. 33.1 A 16nm 32Mb Embedded STT-MRAM with a 6ns Read-Access Time, a 1M-Cycle Write Endurance, 20-Year Retention at 150°C and MTJ-OTP Solutions for Magnetic Immunity
3. Smart Hammering: A practical method of pinhole detection in MRAM memories
4. Heterogeneous Integration in the AI Era;Kengeri
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