Parallel-Check Trimming Test Approach for Selecting the Reference Resistance of STT-MRAMs
Author:
Affiliation:
1. National Central University,Advanced Reliable Systems (ARES) Lab.,Department of Electrical Engineering,Taoyuan,Taiwan,320
Funder
National Science and Technology Council
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx8/10567048/10567052/10567888.pdf?arnumber=10567888
Reference11 articles.
1. Spin-Transfer Torque Memories: Devices, Circuits, and Systems
2. A Test Method for Finding Boundary Currents of 1T1R Memristor Memories
3. A fully-functional 90nm 8Mb STT MRAM demonstrator featuring trimmed, reference cell-based sensing
4. Logic Process Compatible 40-nm 16-Mb, Embedded Perpendicular-MRAM With Hybrid-Resistance Reference, Sub-$\mu$ A Sensing Resolution, and 17.5-nS Read Access Time
5. MBIST Support for Reliable eMRAM Sensing
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