Device Feasibility of 60-nm-Scaled Vertical-Channel Memory Transistors Using InGaZnO Channel and ZnO Charge-Trap Layers
Author:
Affiliation:
1. Department of Advanced Materials Engineering for Information and Electronics, Kyung Hee University, Yongin, South Korea
2. NCD Company Ltd., Daejeon, South Korea
3. Electronics and Telecommunications Research Institute, Daejeon, South Korea
Funder
Technology Innovation Program
Ministry of Trade, Industry and Energy
National Research Foundation of Korea
Korean Government [Ministry of Science and ICT (MSIT)]
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Link
http://xplorestaging.ieee.org/ielx7/16/10457976/10401000.pdf?arnumber=10401000
Reference24 articles.
1. Review of Semiconductor Flash Memory Devices for Material and Process Issues
2. Scaling directions for 2D and 3D NAND cells
3. Review of recent developments in amorphous oxide semiconductor thin-film transistor devices
4. Room-temperature fabrication of transparent flexible thin-film transistors using amorphous oxide semiconductors
5. High-mobility thin-film transistor with amorphous InGaZnO4 channel fabricated by room temperature rf-magnetron sputtering
Cited by 2 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Insights on Asymmetrical Electrode Geometric Effect to Enhance Gate-Drain-Bias Stability of Vertical-Channel InGaZnO Thin-Film Transistor;Electronic Materials Letters;2024-07-30
2. Strong Immunity to Drain-Induced Barrier Lowering in ALD-Grown Preferentially Oriented Indium Gallium Oxide Transistors;ACS Applied Materials & Interfaces;2024-04-25
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