Insights on Asymmetrical Electrode Geometric Effect to Enhance Gate-Drain-Bias Stability of Vertical-Channel InGaZnO Thin-Film Transistor
Author:
Funder
Ministry of Trade, Industry and Energy
Ministry of Science and ICT, South Korea
Publisher
Springer Science and Business Media LLC
Link
https://link.springer.com/content/pdf/10.1007/s13391-024-00513-z.pdf
Reference29 articles.
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2. Cho, Y.J., Kwon, Y.H., Seong, N.J., Choi, K.J., Kim, H.O., Yang, J.H., Hwang, C.S., Yoon, S.M.: Device feasibility of 60-nm-scaled vertical-channel memory transistors Using InGaZnO channel and ZnO charge-trap layers. IEEE Trans. Electron Devices 71, 1839–1844 (2024)
3. Duan, X., Huang, K., Feng, J., Niu, J., Qin, H., Yin, S., Jiao, G., Leonelli, D., Zhao, X., Wang, Z., Wu, Y., Xu, J., Chen, Q., Chuai, X., Lu, C., Wang, W., Yang, G.: Novel vertical channel-all-around (CAA) In-Ga-Zn-O FET for 2T0C-DRAM with high density beyond 4F2by monolithic stacking. IEEE Trans. Electron Devices 69, 2196–2202 (2022)
4. Seidel, K.F., Rossi, L., Jastrombek, D., Kalinowski, H.J.: Vertical organic field effect transistor: on–off state definition related to ambipolar gate biasing. Appl. Phys. A Mater. Sci. Process (2018). https://doi.org/10.1007/s00339-018-1982-x
5. Nogueira, G.L., da Silva Ozório, M., da Silva, M.M., Morais, R.M., Alves, N.: Middle electrode in a vertical transistor structure using an sn layer by thermal evaporation. Electron. Mater. Lett. 14, 319–327 (2018)
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