Performance Analysis of DMG-GOS Junctionless FinFET with high-k Spacer
Author:
Affiliation:
1. VIT-AP University,School of Electronics Engineering,Amaravati,Andhra Pradesh,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10028779/10028780/10028902.pdf?arnumber=10028902
Reference29 articles.
1. A novel bottom-spacer ground-plane (BSGP) FinFET for improved logic and analog/RF performance
2. Dual-material gate (DMG) field effect transistor
3. A Comprehensive Analysis of Junctionless Tri-Gate (TG) FinFET Towards Low-Power and High-Frequency Applications at 5-nm Gate Length
4. Design and Deep Insights into Sub-10 nm Spacer Engineered Junctionless FinFET for Nanoscale Applications;sreenivasulu;ECS J Solid State Sci Technol,2021
5. Analytical modeling and simulation of multigate FinFET devices and the impact of high-k dielectrics on short channel effects (SCEs)
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1. Effect of Work Function Modulation on Switching Current Ratio For A Dual Metal Gate Junctionless FinFET(DMG-JL FinFET);2023 International Conference on Next Generation Electronics (NEleX);2023-12-14
2. Influence of Temperature Fluctuations on the Analog and RF Characteristics of Gate-Engineered High-K Gate Dielectric Stack SOI Fin-FET;2023 IEEE 3rd International Conference on Applied Electromagnetics, Signal Processing, & Communication (AESPC);2023-11-24
3. Design of highly stable, high speed and low power 10T SRAM cell in 18-nm FinFET technology;Engineering Research Express;2023-09-01
4. Effect of Wfin, Hfin and Lg on the performance of 14-nm FinFET for analog and RF applications;2023 International Conference on Device Intelligence, Computing and Communication Technologies, (DICCT);2023-03-17
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