Influence of Temperature Fluctuations on the Analog and RF Characteristics of Gate-Engineered High-K Gate Dielectric Stack SOI Fin-FET
Author:
Affiliation:
1. School of Electronics Engineering, VIT-AP University,Amaravati,Andhra pradesh,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10389813/10389825/10389869.pdf?arnumber=10389869
Reference26 articles.
1. Effect of gate dielectric on electrical parameters due to metal gate WFV in n‐channel Si step FinFET
2. Performance Analysis of DMG-GOS Junctionless FinFET with high-k Spacer
3. A Comprehensive Review on FinFET in Terms of its Device Structure and Performance Matrices
4. A Comprehensive Analysis of Junctionless Tri-Gate (TG) FinFET Towards Low-Power and High-Frequency Applications at 5-nm Gate Length
5. Scaling of Trigate Junctionless Nanowire MOSFET With Gate Length Down to 13 nm
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