Impact of Geometrical and Process Design Parameters on the Performance of Schottky Barrier Reconfigurable Field Effect Transistor
Author:
Affiliation:
1. Islamic Azad University,Yadegar-e-Imam Khomeini (RAH) Shahr-e-Rey Branch,Department of Electronic,Tehran,Iran
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10443089/10443077/10443117.pdf?arnumber=10443117
Reference13 articles.
1. Improved Drain Current with Suppressed Short Channel Effect of p + Pocket Double-Gate MOSFET in Sub-14 nm Technology Node
2. Advanced Short-Channel-Effect Modeling With Applicability to Device Optimization—Potentials and Scaling
3. The past and future of multi-gate field-effect transistors: Process challenges and reliability issues
4. Study of a hysteresis window of FinFET and fully-depleted silicon-on-insulator (FDSOI) MOSFET with ferroelectric capacitor
5. Millimeter-Wave Vertical III-V Nanowire MOSFET Device-to-Circuit Co-Design
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