Improved Drain Current with Suppressed Short Channel Effect of p + Pocket Double-Gate MOSFET in Sub-14 nm Technology Node
Author:
Publisher
Springer Science and Business Media LLC
Subject
Electronic, Optical and Magnetic Materials
Link
https://link.springer.com/content/pdf/10.1007/s12633-022-01816-2.pdf
Reference32 articles.
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3. Bashir MY, Raushan MA, Ahmad S et al (2021) Investigation of gate material engineering in junctionless transistor for digital and analog applications. Silicon. https://doi.org/10.1007/s12633-021-01066-8
4. Mendiratta N, Tripathi SL (2020) A review on performance comparison of advanced MOSFET structures below 45 nm technology node. J Semicond 41:061401. https://doi.org/10.1088/1674-4926/41/6/061401
5. Kumar S, Raj B, Raj B (2021) Dual-material gate-drain overlapped DG-TFET device for low leakage current design. Silicon 13:1599–1607
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