1. The silicon insulated-gate field-effect transistor;Hofstein;Proc IEEE,1963
2. Cramming more components onto integrated circuits;Moore;Electronics,1965
3. A 90-nm logic technology featuring strained-silicon;Thompson;IEEE Trans Electron Devices,2004
4. A 45 nm logic technology with high-k metal gate transistors, strained silicon, 9 Cu interconnect layers, 193nm dry patterning, and 100% Pb-free packaging;Mistry;IEEE International Electron Devices Meeting,2007
5. A 22 nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors;Auth;Symp VLSI Technol VLSIT,2012