3DNAND GIDL-Assisted Body Biasing for Erase Enabling CMOS under Array (CUA) Architecture-Reference-Cited by-同舟云学术

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3DNAND GIDL-Assisted Body Biasing for Erase Enabling CMOS under Array (CUA) Architecture

Published:2017-05 Issue: Volume: Page:
ISSN:
Container-title:2017 IEEE International Memory Workshop (IMW)
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Author:

Caillat Christian,Beaman Kevin,Bicksler Andrew,Camozzi Elisa,Ghilardi Tecla,Huang Guangyu,Liu Haitao,Liu Yifen,Mao Duo,Mujumdar Salil,Righetti Niccolo,Ulrich Matt,Venkatasubramanian Chandru,Yang Xiangyu,Goda Akira,Gowda Srivardhan,Mebrahtu Henok,Sanda Hiroyuki,Yuwen Yu,Koval Randy

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/7938567/7939058/07939067.pdf?arnumber=7939067

Cited by 20 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Impact of Program–Erase Operation Intervals at Different Temperatures on 3D Charge-Trapping Triple-Level-Cell NAND Flash Memory Reliability;Micromachines;2024-08-23

2. SiGe/Si Heterojunction Drain Transistor for Faster 3D NAND Flash Memory Erase;2024 IEEE International Memory Workshop (IMW);2024-05-12

3. A Heterogeneous Platform for 3D NAND-Based In-Memory Hyperdimensional Computing Engine for Genome Sequencing Applications;IEEE Transactions on Circuits and Systems I: Regular Papers;2024-04

4. Reliability Improvement in Vertical NAND Flash Cells Using Adaptive Incremental Step Pulse Programming (A-ISPP) and Incremental Step Pulse Erasing (ISPE);IEEE Transactions on Electron Devices;2024-03

5. A Novel Channel Preparation Scheme to Optimize Program Disturbance in Three-Dimensional NAND Flash Memory;Micromachines;2024-01-31

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