A Multi-Stage CTLE Design and Optimization for PCI Express Gen6.0 Link Equalization-Reference-Cited by-同舟云学术

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A Multi-Stage CTLE Design and Optimization for PCI Express Gen6.0 Link Equalization

Published:2023-07-03 Issue: Volume: Page:
ISSN:
Container-title:2023 IEEE Latin American Electron Devices Conference (LAEDC)
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Author:

López-Araiza Karla G.¹,Rangel-Patiño Francisco E.¹,Ascencio-Blancarte Jorge E.¹,Vega-Ochoa Edgar A.¹,Rayas-Sánchez José E.²,Longoria-Gandara Omar²

Affiliation:

1. Intel Corp,Zapopan,Jalisco,Mexico,45019

2. ITESO - The Jesuit University of Guadalajara,Systems, and Informatics,Department of Electronics,Tlaquepaque,Jalisco,Mexico,45604

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10209097/10208282/10209113.pdf?arnumber=10209113

Reference11 articles.

1. Direct optimization of a PCI express link equalization in industrial post-silicon validation

2. The design of continuous-time linear equalizers using model order reduction techniques

3. A 32Gb/s wireline receiver with a low-frequency equalizer, CTLE and 2-tap DFE in 28nm CMOS

4. A 2ndorder CTLE in 130nm SiGe BiCMOS for a 50GBaud PAM4 optical driver;he;IEEE Int Conf Integr Circ Tech Applic,2018

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. PCIe Gen6 Physical Layer Equalization Tuning by Using Unsupervised and Supervised Machine Learning Techniques;2023 IEEE MTT-S Latin America Microwave Conference (LAMC);2023-12-06

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