PCIe Gen6 Physical Layer Equalization Tuning by Using Unsupervised and Supervised Machine Learning Techniques
Author:
Affiliation:
1. Intel Corp.,Zapopan,Jalisco,Mexico,45019
2. The Jesuit University of Guadalajara,ITESO,Tlaquepaque,Jalisco,Mexico,45604
3. Intel Corp.,Folsom,CA,USA,95630
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10375531/10375532/10375599.pdf?arnumber=10375599
Reference16 articles.
1. A Holistic Formulation for System Margining and Jitter Tolerance Optimization in Industrial Post-Silicon Validation
2. Transmitter and Receiver Equalizers Optimization Methodologies for High-Speed Links in Industrial Computer Platforms Post-Silicon Validation
3. Direct optimization of a PCI express link equalization in industrial post-silicon validation
4. Post-Silicon Receiver Equalization Metamodeling by Artificial Neural Networks
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