Design with low complexity fine-grained Dual Core Lock-Step (DCLS) RISC-V processors-Reference-Cited by-同舟云学术

Design with low complexity fine-grained Dual Core Lock-Step (DCLS) RISC-V processors

Published:2023-06 Issue: Volume: Page:
ISSN:
Container-title:2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks - Supplemental Volume (DSN-S)
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Author:

Nikiema Pegdwende Romaric¹,Kritikakou Angeliki¹,Traiola Marcello¹,Sentieys Olivier¹

Affiliation:

1. Inria, Univ Rennes, CNRS, IRISA

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10206428/10206485/10206674.pdf?arnumber=10206674

Reference17 articles.

1. DuckCore: A Fault-Tolerant Processor Core Architecture Based on the RISC-V ISA

2. A Dual Lockstep Processor System-on-a-Chip for Fast Error Recovery in Safety-Critical Applications

3. Neutron Radiation Testing of Fault Tolerant RISC-V Soft Processor on Xilinx SRAM-based FPGAs

4. A RISC-V fault-tolerant microcontroller core architecture based on a hardware thread full/partial protection and a thread-controlled watch-dog timer;blasi;APPLEPIES,2019

5. Dara: A low-cost reliable architecture based on unhardened devices and its case study of radiation stress test;yao;IEEE TNS,2012

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1. Dynamic Triple Modular Redundancy in Interleaved Hardware Threads: An Alternative Solution to Lockstep Multi-Cores for Fault-Tolerant Systems;IEEE Access;2024

2. On-Chip Bus Protection against Soft Errors;Electronics;2023-11-19

3. SafeLS: An Open Source Implementation of a Lockstep NOEL-V RISC-V Core;2023 IEEE 29th International Symposium on On-Line Testing and Robust System Design (IOLTS);2023-07-03

4. Towards Dependable RISC-V Cores for Edge Computing Devices;2023 IEEE 29th International Symposium on On-Line Testing and Robust System Design (IOLTS);2023-07-03