Dynamic Triple Modular Redundancy in Interleaved Hardware Threads: An Alternative Solution to Lockstep Multi-Cores for Fault-Tolerant Systems
Author:
Affiliation:
1. Department of Information Engineering, Electronics and Telecommunications (DIET), Sapienza University of Rome, Rome, Italy
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Link
http://xplorestaging.ieee.org/ielx8/6287639/10380310/10589631.pdf?arnumber=10589631
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1. Optimal NBTI degradation and PVT variation resistant device sizing in a full adder cell
2. Downsizing Effects on Micro and Nano Comb Drives
3. A RISC-V Fault-Tolerant Microcontroller Core Architecture Based on a Hardware Thread Full/Partial Protection and a Thread-Controlled Watch-Dog Timer
4. Analysis of a Fault Tolerant Edge-Computing Microarchitecture Exploiting Vector Acceleration
5. Reduced-Order Observer-Based Finite Time Fault Estimation for Switched Systems With Lager and Fast Time Varying Fault
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