A RISC-V Fault-Tolerant Microcontroller Core Architecture Based on a Hardware Thread Full/Partial Protection and a Thread-Controlled Watch-Dog Timer-Reference-Cited by-同舟云学术

A RISC-V Fault-Tolerant Microcontroller Core Architecture Based on a Hardware Thread Full/Partial Protection and a Thread-Controlled Watch-Dog Timer

Published:2020 Issue: Volume: Page:505-511
ISSN:1876-1100
Container-title:Lecture Notes in Electrical Engineering
language:
Short-container-title:

Author:

Blasi Luigi,Vigli Francesco,Cheikh Abdallah,Mastrandrea Antonio,Menichelli Francesco,Olivieri Mauro

Publisher

Springer International Publishing

Link

http://link.springer.com/content/pdf/10.1007/978-3-030-37277-4_59

Reference10 articles.

1. ESA-ESTEC (2016) Space product assurance—techniques for radiation effects mitigation in ASICs and FPGAs handbook. ECSS-Q-HB-60-02A

2. RISC-V User-Level ISA Specification v2.2, Online: https://riscv.org/specifications/

3. RISC-V Privileged ISA Specification v1.10, Online: https://riscv.org/specifications/privileged-isa/

4. Gupta S, Gala N, Madhusudan G, Kamakoti V (2015) SHAKTI-F: a fault tolerant microprocessor architecture. In: IEEE 24th Asian test symposium

5. Blasi L, Mastrandrea A, Menichelli F, Olivieri M (2018) A space-rated soft IP-core compatible with the PIC® hardware architecture and instruction set. Adv Astronaut Sci 163:581–594

Cited by 5 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Dynamic Triple Modular Redundancy in Interleaved Hardware Threads: An Alternative Solution to Lockstep Multi-Cores for Fault-Tolerant Systems;IEEE Access;2024

2. A RISC-V Fault-Tolerant Soft-Processor Based on Full/Partial Heterogeneous Dual-Core Protection;IEEE Access;2024

3. SecDec: Secure Decode Stage thanks to masking of instructions with the generated signals;2022 25th Euromicro Conference on Digital System Design (DSD);2022-08

4. Fault resilience analysis of a RISC-V microprocessor design through a dedicated UVM environment;2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT);2020-10-19

5. Efficient Mathematical Accelerator Design Coupled with an Interleaved Multi-threading RISC-V Microprocessor;Lecture Notes in Electrical Engineering;2020