Design of low power 4-bit flash ADC based on standard cells
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Publisher
IEEE
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http://xplorestaging.ieee.org/ielx7/6568396/6573561/06573626.pdf?arnumber=6573626
Cited by 11 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. A 86 mW of Power, 1.57 dB of Noise Figure, Low-IF CMOS Receiver Front End for Sub-6 GHz Applications;2024 3rd International Conference for Innovation in Technology (INOCON);2024-03-01
2. Design of High Performance and Power Efficient Flash ADC;International Journal of Scientific Research in Science and Technology;2023-04-01
3. Realization of a variable resolution modified semiflash ADC based on bit segmentation scheme;Facta universitatis - series: Electronics and Energetics;2022
4. Power Saving Scheme for Process Corner Calibrated Standard Cell Based Flash ADC in Wireless Surveillance Applications;SN Computer Science;2020-09-26
5. Design of a 4-Bit Wallace Tree Encoder for Flash ADC in 90 Nm CMOS Technology;Lecture Notes in Electrical Engineering;2020-09-20
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