Design of a 4-Bit Wallace Tree Encoder for Flash ADC in 90 Nm CMOS Technology
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Publisher
Springer Singapore
Link
http://link.springer.com/content/pdf/10.1007/978-981-15-5546-6_80
Reference16 articles.
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3. Babayan-Mashhadi S, Lotfi R (2014) Analysis and design of a low-voltage low-power double-tail comparator. IEEE Trans Very Large Scale Integr (VLSI) Syst 22(2):343–352
4. Patil H, Raghavendra M (2016) Low power dynamic comparator for 4-bit flash ADC. In: 2016 IEEE international conference on computational intelligence and computing research (ICCIC)
5. Mayur SM, Siddharth RK, Kumar YBN, Vasantha MH (2016) Design of low power 5-bit hybrid flash ADC. In: 2016 IEEE computer society annual symposium on VLSI
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