Design of Low Power 5-Bit Hybrid Flash ADC-Reference-Cited by-同舟云学术

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Design of Low Power 5-Bit Hybrid Flash ADC

Published:2016-07 Issue: Volume: Page:
ISSN:
Container-title:2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
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Author:

Mayur S.M.,Siddharth R.K.,Nithin Kumar Y.B.,Vasantha M.H.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/7558446/7560148/07560221.pdf?arnumber=7560221

Cited by 12 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Design of AD Converters in 0.35 µm SiGe BiCMOS Technology for Ultra-Wideband M-Sequence Radar Sensors;Sensors;2024-04-29

2. Comparison of Low Power High Speed Comparator for Flash ADC;Highlights in Science, Engineering and Technology;2023-02-12

3. A Novel Rail-to-Rail Input Swing Threshold-Inverter Multi-Bit Quantizer Using Interpolation Technique for Sampled-Data Circuits;Journal of Circuits, Systems and Computers;2021-09-29

4. Power Saving Scheme for Process Corner Calibrated Standard Cell Based Flash ADC in Wireless Surveillance Applications;SN Computer Science;2020-09-26

5. Design of a 4-Bit Wallace Tree Encoder for Flash ADC in 90 Nm CMOS Technology;Lecture Notes in Electrical Engineering;2020-09-20

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