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Hot-Carrier-Induced Degradations and Optimizations for Lateral DMOS Transistor With Multiple Floating Poly-Gate Field Plates

  • Published:2017-08 Issue:8 Volume:64 Page:3275-3281
  • ISSN:0018-9383
  • Container-title:IEEE Transactions on Electron Devices
  • language:
  • Short-container-title:IEEE Trans. Electron Devices

Author:

Liu Siyang,Ren Xiaofei,Fang Yunchao,Sun WeifengORCID,Su Wei,Ma Shulang,Lin Feng,Liu Yuwei,Sun Guipeng

Funder

National Natural Science Foundation of China

Natural Science Foundation of Jiangsu Province

Qinglan Project

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Cited by 15 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Study of Turns Impact on ESD-immunity of High-voltage nLDMOSs with a Constant Floating-poly;2022 IEEE 4th Eurasia Conference on IOT, Communication and Engineering (ECICE);2022-10-28

2. Drain-extended MOS design using High-k dielectric to control off-state BTBT with enhanced switching performance;Engineering Research Express;2022-07-27

3. Optimizing 20V LDNMOS Transistors for PMIC Applications by Simulation Tools;2022 IEEE International Conference on Consumer Electronics - Taiwan;2022-07-06

4. Experiments of Homogenization Field LDMOS With Trench-Stopped Depletion;IEEE Transactions on Electron Devices;2022-05

5. Study on 20 V LDMOS With Stepped-Gate-Oxide Structure for PMIC Applications: Design, Fabrication, and Characterization;IEEE Transactions on Electron Devices;2022-02
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