A Multi-Bit In-Memory-Computing SRAM Macro Using Column-Wise Charge Redistribution for DNN Inference in Edge Computing Devices-Reference-Cited by-同舟云学术

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A Multi-Bit In-Memory-Computing SRAM Macro Using Column-Wise Charge Redistribution for DNN Inference in Edge Computing Devices

Published:2021-10-06 Issue: Volume: Page:
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Container-title:2021 18th International SoC Design Conference (ISOCC)
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Author:

Chae Changseon,Kim Subin,Choi Jonghang,Park Jun-Eun

Funder

National Research Foundation

Ministry of Education

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9613844/9613845/09613934.pdf?arnumber=9613934

Cited by 4 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. An N-Type Pseudo-Static eDRAM Macro with Reduced Access Time for High-Speed Processing-in-Memory in Intelligent Sensor Hub Applications;Sensors;2023-11-22

2. Reconfigurable Compute in Memory Using SRAM and Bit Serial Algorithm;2023 5th International Conference on Inventive Research in Computing Applications (ICIRCA);2023-08-03

3. A Column-Parallel Time-Interleaved SAR/SS ADC for Computing in Memory with 2-8bit Reconfigurable Resolution;2023 IEEE 5th International Conference on Artificial Intelligence Circuits and Systems (AICAS);2023-06-11

4. Pseudo-Static Gain Cell of Embedded DRAM for Processing-in-Memory in Intelligent IoT Sensor Nodes;Sensors;2022-06-04

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