A high speed low noise CMOS dynamic full adder cell-Reference-Cited by-同舟云学术

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A high speed low noise CMOS dynamic full adder cell

Published:2013-12 Issue: Volume: Page:
ISSN:
Container-title:2013 International conference on Circuits, Controls and Communications (CCUBE)
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Author:

Meher Preetisudha,Mahapatra Kamala Kanta

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/6710230/6718537/06718575.pdf?arnumber=6718575

Cited by 4 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. 4×4 Array Multiplier Using Transmission Gate Full Adder;2024 IEEE 9th International Conference for Convergence in Technology (I2CT);2024-04-05

2. Low-Power High-Performance Hybrid Scalable;Proceedings of First International Conference on Computational Electronics for Wireless Communications;2022

3. A novel ultra-low-power gate overlap tunnel FET (GOTFET) dynamic adder;International Journal of Electronics;2020-03-26

4. Performance analysis of dynamic CMOS circuit based on node‐discharger and twist‐connected transistors;IET Computers & Digital Techniques;2020-02-10

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