A novel ultra-low-power gate overlap tunnel FET (GOTFET) dynamic adder
Author:
Affiliation:
1. Department of Electrical & Electronics Engineering, Birla Institute of Technology and Science Pilani, Hyderabad, India
Publisher
Informa UK Limited
Subject
Electrical and Electronic Engineering
Link
https://www.tandfonline.com/doi/pdf/10.1080/00207217.2020.1740800
Reference33 articles.
1. Analysis of Leakage in 32-Bit Adders in 45 nm Technology
2. Analysis of Cylindrical Gate Junctionless Tunnel Field Effect Transistor (CG-JL-TFET)
3. TFET Inverters With n-/p-Devices on the Same Technology Platform for Low-Voltage/Low-Power Applications
4. Line Tunneling Dominating Charge Transport in SiGe/Si Heterostructure TFETs
5. Heterojunction fully depleted SOI-TFET with oxide/source overlap
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