Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation—Part II: CNT Interconnect Optimization-Reference-Cited by-同舟云学术

Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation—Part II: CNT Interconnect Optimization

Published:2022-04 Issue:4 Volume:30 Page:440-448
ISSN:1063-8210
Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
language:
Short-container-title:IEEE Trans. VLSI Syst.

Author:

Chen Rongmei¹^ORCID,Chen Lin²,Liang Jie³^ORCID,Cheng Yuanqing²^ORCID,Elloumi Souhir⁴,Lee Jaehyun⁵^ORCID,Xu Kangwei²,Georgiev Vihar P.⁶^ORCID,Ni Kai⁷^ORCID,Debacker Peter¹^ORCID,Asenov Asen⁶,Todri-Sanial Aida⁴^ORCID

Affiliation:

1. IMEC, Leuven, Belgium

2. School of Microelectronics, Beihang University, Beijing, China

3. School of Microelectronics, Shanghai University, Shanghai, China

4. Department of Microelectronics, Laboratory of Computer Science, Robotics and Microelectronics of Montpellier (LIRMM), University of Montpellier, CNRS, Montpellier, France

5. Synopsys, Ltd., Glasgow, U.K.

6. School of Engineering, University of Glasgow, Glasgow, U.K.

7. Department of Microsystems, Rochester Institute of Technology, Rochester, NY, USA

Funder

European Commission H2020 CONNECT Project

Marie Skłodowska-Curie Individual Fellowship

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

http://xplorestaging.ieee.org/ielx7/92/9739817/09714073.pdf?arnumber=9714073