DC/AC Performance Boosting with Sub 5-nm Semiconductor Technology Node
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Publisher
Springer Nature Singapore
Link
https://link.springer.com/content/pdf/10.1007/978-981-99-6649-3_54
Reference7 articles.
1. Tang Y-T, et al. A comprehensive study of polymorphic phase distribution of ferroelectric-dielectrics and interfacial layer effects on negative capacitance FETs for sub-5 nm node. In: 2018 IEEE symposium on VLSI technology, Honolulu, HI, USA; 2018. p. 45–6. https://doi.org/10.1109/VLSIT.2018.8510696.
2. Huynh-Bao T, et al. Statistical timing analysis considering device and interconnect variability for BEOL requirements in the 5-nm node and beyond. IEEE Trans Very Large Scale Integr (VLSI) Syst. 2017;25(5):1669–80. https://doi.org/10.1109/TVLSI.2017.2647853.
3. Chen R, et al. Carbon nanotube SRAM in 5-nm technology node design, optimization, and performance evaluation – part I: CNFET transistor optimization. IEEE Trans Very Large Scale Integr (VLSI) Syst. 2022;30(4):432–9. https://doi.org/10.1109/TVLSI.2022.3146125.
4. Chen R, et al. Carbon nanotube SRAM in 5-nm technology node design, optimization, and performance evaluation – part II: CNT interconnect optimization. IEEE Trans Very Large Scale Integr (VLSI) Syst. 2022;30(4):440–8. https://doi.org/10.1109/TVLSI.2022.3146064.
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