Design of Low-Power Operation with Sub 7-nm Semiconductor Technology Node
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Publisher
Springer Nature Singapore
Link
https://link.springer.com/content/pdf/10.1007/978-981-99-6649-3_55
Reference8 articles.
1. Chen JH-C, Standaert TE, Alptekin E, Spooner TA, Paruchuri V. Interconnect performance and scaling strategy at 7 nm node. In: IEEE international interconnect technology conference, San Jose, CA, USA; 2014. p. 93–6. https://doi.org/10.1109/IITC.2014.6831843.
2. Chang K, Acharya K, Sinha S, Cline B, Yeric G, Lim SK. Impact and design guideline of monolithic 3-D IC at the 7-nm technology node. IEEE Trans Very Large Scale Integr (VLSI) Syst. 2017;25(7):2118–29. https://doi.org/10.1109/TVLSI.2017.2686426.
3. Ko C-T, Kuan T-K, Shen R-P, Chang C-H. A 7-nm FinFET CMOS PLL with 388-fs jitter and −80-dBc reference spur featuring a track-and-hold charge pump and automatic loop gain control. IEEE J Solid State Circuits. 2020;55(4):1043–50. https://doi.org/10.1109/JSSC.2019.2959735.
4. Rathore S, et al. Self-heating aware threshold voltage modulation conforming to process and ambient temperature variation for reliable nanosheet FET. In: 2023 IEEE international reliability physics symposium (IRPS), Monterey, CA, USA; 2023. p. 1–5. https://doi.org/10.1109/IRPS48203.2023.10117918.
5. Chen R, et al. Carbon nanotube SRAM in 5-nm technology node design, optimization, and performance evaluation – part II: CNT interconnect optimization. IEEE Trans Very Large Scale Integr (VLSI) Syst. 2022;30(4):440–8. https://doi.org/10.1109/TVLSI.2022.3146064.
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