Correlation Aware Random Pattern Generation for Test Time and Shift Power Reduction of Logic BIST
Author:
Affiliation:
1. Yonsei University,Dept. of Electrical and Electronic Engineering,Seoul,Korea
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10031262/10031265/10031357.pdf?arnumber=10031357
Reference5 articles.
1. A Low-Power BIST Scheme Using Weight-Aware Scan Grouping and Scheduling for Automotive ICs
2. Energy-Efficient Scheme for Multiple Scan-Chains BIST Using Weight-Based Segmentation
3. Static compaction techniques to control scan vector power dissipation
4. Low-Power Scan-Based Built-In Self-Test Based on Weighted Pseudorandom Test Pattern Generation and Reseeding
5. Hybrid BIST based on weighted pseudo-random testing: a new test resource partitioning scheme
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