A 4nm 32Gb/s 8Tb/s/mm Die-to-Die Chiplet Using NRZ Single-Ended Transceiver With Equalization Schemes And Training Techniques-Reference-Cited by-同舟云学术

A 4nm 32Gb/s 8Tb/s/mm Die-to-Die Chiplet Using NRZ Single-Ended Transceiver With Equalization Schemes And Training Techniques

Published:2023-02-19 Issue: Volume: Page:
ISSN:
Container-title:2023 IEEE International Solid- State Circuits Conference (ISSCC)
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Author:

Seong Kihwan¹,Park Donguk¹,Bae Gyeomje¹,Lee Hyunwoo¹,Suh Youngseob¹,Oh Wooseuk¹,Lee Hyemun¹,Kim Juyoung¹,Lee Takgun¹,Mo Geonhoo¹,Jung Sukhyun¹,Choi Dongcheol¹,Yoo Byoung-Joo¹,Park Sanghune¹,Rhew Hyo-Gyuem¹,Shin Jongshin¹

Affiliation:

1. Samsung Electronics,Hwasung,Korea

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10067248/10067251/10067477.pdf?arnumber=10067477

Reference6 articles.

1. A 7nm 0.46pJ/bit 20Gbps with BER 1 E-25 Die-to-Die Link Using Minimum Intrinsic Auto Alignment and Noise-Immunity Encode;hus;IEEE Symp VLSI Technology,2021

2. A 1.6Tb/s Chiplet over XSR-MCM Channels using 113Gb/s PAM-4 Transceiver with Dynamic Receiver-Driven Adaptation of TX-FFE and Programmable Roaming Taps in 5nm CMOS;gangasani;ISSCC,2022

3. A 7.8-Gb/s 2.9-pJ/b Single-Ended Receiver With 20-Tap DFE for Highly Reflective Channels

4. A 0.297-pJ/bit 50.4-Gb/s/wire Inverter-Based Short-Reach Simultaneous Bidirectional Transceiver for Die-to-Die Interface in 5nm CMOS

5. 11.3 A 480Gb/s/mm 1.7pJ/b Short-Reach Wireline Transceiver Using Single-Ended NRZ for Die-to-Die Applications

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