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A 7.8-Gb/s 2.9-pJ/b Single-Ended Receiver With 20-Tap DFE for Highly Reflective Channels

  • Published:2020-03 Issue:3 Volume:28 Page:818-822
  • ISSN:1063-8210
  • Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  • language:
  • Short-container-title:IEEE Trans. VLSI Syst.

Author:

Seo JaeyoungORCID,Ko Jaehyun,Lim Kyunghyun,Lee SooeunORCID,Sim Jae-YoonORCID,Park Hong-JuneORCID,Kim ByungsubORCID

Funder

National Research Foundation of Korea

Institute of Information & Communications Technology Planning & Evaluation (IITP) Grant funded by the Ministry of Science and ICT (MSIT), Korea

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Cited by 9 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A PAM-4 Crosstalk Compensation Receiver Using an RC Circuit per Pin for $4\times 24$ Gb/s/Pin Single-Ended DRAM Interface;IEEE Transactions on Circuits and Systems I: Regular Papers;2024

2. Thresholding Decision-Directed Descent (T3D): A Tuning Solution for DDR5 DRAM DFEs;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2024

3. A 4nm 32Gb/s 8Tb/s/mm Die-to-Die Chiplet Using NRZ Single-Ended Transceiver With Equalization Schemes And Training Techniques;2023 IEEE International Solid- State Circuits Conference (ISSCC);2023-02-19

4. A Reflection Self-Canceling Design Technique for Multidrop Memory Interfaces;IEEE Transactions on Components, Packaging and Manufacturing Technology;2022-11

5. A power‐efficient current‐integrating hybrid for full‐duplex communication over chip‐to‐chip interconnects;International Journal of Circuit Theory and Applications;2022-07-27
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