Leveraging Micro-Bump Pitch Scaling to Accelerate Interposer Link Bandwidths for Future High-Performance Compute Applications-Reference-Cited by-同舟云学术

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Leveraging Micro-Bump Pitch Scaling to Accelerate Interposer Link Bandwidths for Future High-Performance Compute Applications

Published:2024-04-21 Issue: Volume: Page:1-7
ISSN:
Container-title:2024 IEEE Custom Integrated Circuits Conference (CICC)
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Author:

Turner Walker J.¹,Poulton John W.¹,Nishi Yoshinori²,Chen Xi²,Zimmer Brian²,Song Sanquan²,Wilson John M.¹,Dally William J.²,Gray C. Thomas¹

Affiliation:

1. NVIDIA,Durham,NC

2. NVIDIA,Santa Clara,CA

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10528947/10528954/10529010.pdf?arnumber=10529010

Reference7 articles.

1. MCM/Chiplet Solutions;Naffziger;ISSCC 2021 Forum on Enabling New System Architectures with 2.5, 3D and Chiplet Technologies,2021

2. High-NA EUV Progress and Outlook;Van Schoot,2021

3. CoWoS Architecture Evolution for Next Generation HPC on 2.5D System in Package

4. A 7nm 0.46pJ/bit 20Gbps with BER 1E-25 Die-to-Die Link Using Minimum Intrinsic Auto Alignment and Noise-Immunity Encode;Hsu,2021

5. A 0.190-pJ/bit 25.2-Gb/s/wire Inverter-Based AC-Coupled Transceiver for Short-Reach Die-to-Die Interfaces in 5-nm CMOS

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