10.4 A Rail-to-Rail 12MS 91.3dB SNDR 94.1dB DR Two-Step SAR ADC with Integrated Input Buffer Using Predictive Level-Shifting
Author:
Affiliation:
1. Oregon State University,Corvallis,OR
2. Asahi Kasei Microdevices,Atsugi,Japan
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10067248/10067251/10067703.pdf?arnumber=10067703
Reference7 articles.
1. A 4.5mW CT self-coupled ?? modulator with 2.2MHz BW and 90.4dB SNDR using residual ELD compensation;ho;ISSCC,2015
2. An 18-bit 2MS/s pipelined SAR ADC utilizing a sampling distortion cancellation circuit with −107dB THD at 100kHz
3. A signal-independent background-calibrating 20b 1MS/S SAR ADC with 0.3ppm INL
4. A 14 Bit 1 GS/s RF Sampling Pipelined ADC With Background Calibration
5. 15.7 14b 35MS/S SAR ADC achieving 75dB SNDR and 99dB SFDR with loop-embedded input buffer in 40nm CMOS
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2. Analysis and Calibration of Bit Weights in SAR and Pipelined SAR ADCs Based on Code Distribution;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2024-06
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4. A 1.2-mA Fast-Charge Input Buffer with CLS for 4-MS/s SC Oversampling ADC Achieving +1-2.5-ppm/FSR INL;2023 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA);2023-10-27
5. Design Techniques for Energy-Efficient Analog-to-Digital Converters;IEEE Open Journal of the Solid-State Circuits Society;2023
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