An 18-bit 2MS/s pipelined SAR ADC utilizing a sampling distortion cancellation circuit with −107dB THD at 100kHz
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Publisher
IEEE
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http://xplorestaging.ieee.org/ielx7/8000695/8008441/08008508.pdf?arnumber=8008508
Cited by 13 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Input currents of CMOS SAR ADC in microcontroller, their measurement and behavior model from users point of view;Measurement;2024-08
2. An energy-efficient reconfigurable 18/12-bit 1 MS/s pipelined-SAR ADC;AEU - International Journal of Electronics and Communications;2024-05
3. A Rail-to-Rail 12 MS/s 91.3 dB SNDR 94.1 dB DR Two-Step SAR ADC With Integrated Input Buffer Using Predictive Level-Shifting;IEEE Journal of Solid-State Circuits;2023-12
4. A Foreground LSB-Based Capacitor Mismatch Calibration Method in An 18-bit SAR ADC;2023 IEEE International Symposium on Circuits and Systems (ISCAS);2023-05-21
5. 10.4 A Rail-to-Rail 12MS 91.3dB SNDR 94.1dB DR Two-Step SAR ADC with Integrated Input Buffer Using Predictive Level-Shifting;2023 IEEE International Solid- State Circuits Conference (ISSCC);2023-02-19
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