A Rail-to-Rail 12 MS/s 91.3 dB SNDR 94.1 dB DR Two-Step SAR ADC With Integrated Input Buffer Using Predictive Level-Shifting
Author:
Affiliation:
1. Department of Electrical Engineering and Computer Science (EECS), Oregon State University, Corvallis, OR, USA
2. Asahi Kasei Microdevices Corporation, Atsugi, Japan
Funder
Analog Devices and the Center for Design of Analog-Digital Integrated Circuits
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/4/10328904/10250953.pdf?arnumber=10250953
Reference17 articles.
1. A 61.5 dB SNDR pipelined ADC using simple highly-scalable ring amplifiers;hershberg;Proc Symp VLSI Circuits (VLSIC),2012
2. The flipped voltage follower: a useful cell for low-voltage low-power circuit design
3. A 1-GS/s, 12-b, Single-Channel Pipelined ADC With Dead-Zone-Degenerated Ring Amplifiers
4. A 100 MS/s, 10.5 Bit, 2.46 mW Comparator-Less Pipeline ADC Using Self-Biased Ring Amplifiers
5. An improved correlated double sampling circuit for low noise charge coupled devices
Cited by 4 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. A 16-bit 4-MS/s SAR ADC With Dual-Segmental Bit Weight Self-Calibration;IEEE Transactions on Circuits and Systems I: Regular Papers;2024-09
2. An Easy-to-Drive Discrete-Time ADC Topology Using Digital Predictive Level-Shifting;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19
3. An energy-efficient reconfigurable 18/12-bit 1 MS/s pipelined-SAR ADC;AEU - International Journal of Electronics and Communications;2024-05
4. A Rail-to-Rail 12 MS/s 91.3 dB SNDR 94.1 dB DR Two-Step SAR ADC With Integrated Input Buffer Using Predictive Level-Shifting;IEEE Journal of Solid-State Circuits;2023-12
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