15.7 14b 35MS/S SAR ADC achieving 75dB SNDR and 99dB SFDR with loop-embedded input buffer in 40nm CMOS-Reference-Cited by-同舟云学术

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15.7 14b 35MS/S SAR ADC achieving 75dB SNDR and 99dB SFDR with loop-embedded input buffer in 40nm CMOS

Published:2015-02 Issue: Volume: Page:
ISSN:
Container-title:2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers
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Author:

Kramer Martin,Janssen Erwin,Doris Kostas,Murmann Boris

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/7054075/7062838/07063037.pdf?arnumber=7063037

Cited by 13 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. 10.4 A Rail-to-Rail 12MS 91.3dB SNDR 94.1dB DR Two-Step SAR ADC with Integrated Input Buffer Using Predictive Level-Shifting;2023 IEEE International Solid- State Circuits Conference (ISSCC);2023-02-19

2. An 84dB-SNDR Low-OSR 4^th-Order Noise-Shaping SAR with an FIA-Assisted EF-CRFF Structure and Noise-Mitigated Push-Pull Buffer-in-Loop Technique;2022 IEEE International Solid- State Circuits Conference (ISSCC);2022-02-20

3. A 10b 42MS/s SAR ADC with Power Efficient Design;2021 6th International Conference on Integrated Circuits and Microsystems (ICICM);2021-10-22

4. A SAR ADC with Reduced kT/C Noise by Decoupling Noise PSD and BW;2020 IEEE Symposium on VLSI Circuits;2020-06

5. A Single-Supply Buffer-Embedding SAR ADC with Skip-Reset having Inherent Chopping Capability;2019 IEEE Asian Solid-State Circuits Conference (A-SSCC);2019-11

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