A 1.2-mA Fast-Charge Input Buffer with CLS for 4-MS/s SC Oversampling ADC Achieving +1-2.5-ppm/FSR INL
Author:
Affiliation:
1. School of Microelectronics, XJTU,Xi'an,China
2. Xi'an Aerosemi Technology Co., LTD.,Xi'an,China
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10363774/10363775/10364291.pdf?arnumber=10364291
Reference5 articles.
1. A 60-MS/s 5-MHz BW Noise-Shaping SAR ADC With Integrated Input Buffer Achieving 84.2-dB SNDR and 97.3-dB SFDR Using Dynamic Level-Shifting and ISI-Error Correction
2. A 19 nV/ $\surd$ Hz Noise 2- $\mu \text{V}$ Offset 75- $\mu \text{A}$ Capacitive-Gain Amplifier With Switched-Capacitor ADC Driving Capability
3. A 128ksps 120dB THD Low Noise Analog Front End
4. A 75.3-dB SNDR 24-MS/s Ring Amplifier-Based Pipelined ADC Using Averaging Correlated Level Shifting and Reference Swapping for Reducing Errors From Finite Opamp Gain and Capacitor Mismatch
5. 10.4 A Rail-to-Rail 12MS 91.3dB SNDR 94.1dB DR Two-Step SAR ADC with Integrated Input Buffer Using Predictive Level-Shifting
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