Suppression of Quantization-Induced Convergence Error in Pipelined ADCs With Harmonic Distortion Correction-Reference-Cited by-同舟云学术

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Suppression of Quantization-Induced Convergence Error in Pipelined ADCs With Harmonic Distortion Correction

Published:2013-03 Issue:3 Volume:60 Page:593-602
ISSN:1549-8328
Container-title:IEEE Transactions on Circuits and Systems I: Regular Papers
language:
Short-container-title:IEEE Trans. Circuits Syst. I

Author:

Rakuljic Nevena,Galton Ian

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx5/8919/6468162/06392313.pdf?arnumber=6392313

Cited by 17 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. An interstage gain calibration technique for pipelined ADCs exploiting complementary dithering and calibration windows detector;IEICE Electronics Express;2024-04-25

2. A new digital background calibration technique for pipeline analog to digital converters using decision points of the voltage transfer characteristics;Analog Integrated Circuits and Signal Processing;2023-11-22

3. A 1.5GS/s Single-Channel Pipelined ADC With Large Dither Technique;2023 8th International Conference on Integrated Circuits and Microsystems (ICICM);2023-10-20

4. A Histogram-Based Digital Background Calibration Technique for Pipelined A/D Converters;2022 Iranian International Conference on Microelectronics (IICM);2022-12-20

5. A 16-Bit 120 MS/s Pipelined ADC Using a Multi-Level Dither Technique;Electronics;2022-11-30

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