A 16-Bit 120 MS/s Pipelined ADC Using a Multi-Level Dither Technique

Abstract

In wireless applications, such as radars, tens of MHz signals need to be quantized using an analog-to-digital converter (ADC) with a large dynamic range. The detected signal amplitude can be random, with a small or large amplitude. In addition, the dynamic performance is degraded by capacitor mismatches. A 16-bit 120 MS/s pipelined ADC implemented in a 180 nm complementary metal–oxide–semiconductor (CMOS) process is presented in this work. We propose a multi-level dither technique that can significantly enhance the ADC linearity. The injected dither also helps improve the linearity when the ADC handles an input signal with a small amplitude. Traditional dither injection leads to an increase in the amplifier output swing. A counteracting dither injection scheme, both in sub-flash ADC and the multiplying digital-to-analog converter (MDAC), is proposed to remedy this issue. Moreover, capacitor mismatches in the first three pipeline stages are calibrated in a foreground way. The inter-stage residue gain accuracy is guaranteed by a gain-boosting amplifier. To demonstrate the effectiveness of the dither scheme, we obtained the dynamic performance of the ADC with a small input signal (−12 dBFS). The proposed calibration and dither injection technique improved the spurious-free dynamic range (SFDR) from 77 dBc to 85 dBc with −12 dBFS input. With −1 dBFS input, the SFDR remained at over 85 dBc, reaching up to the Nyquist input frequency. Therefore, the dither scheme enhances the dynamic performance when the ADC handles a signal with small amplitude.