An Accurate and Fast Method for Improving ADC Nonlinearity

Author:

Mohammedali Mohammed Abdulmahdi12ORCID,Al-Gayem Qais2ORCID

Affiliation:

1. College of Health and Medical Techniques, Al-Furat Al-Awsat Technical University, Najaf, Iraq

2. Electrical Engineering Department, College of Engineering, University of Babylon, Hilla, Babil, Iraq

Abstract

Errors in analog-to-digital conversion (ADC) occur due to internal links or other electronic parts; faults that may occur during code conversion cannot be overlooked because signal digitalisation demands a large dynamic range and high resolution. This paper presents a new and accurate self-test method to compensate for one of the most effective errors of ADC because of its effect, which may result in a missing code, which is a differential nonlinear (DNL) of a 10-bit SAR-ADC. The proposed method includes three stages: DNL error modelling for nonideal system implementation, detection, and correction. To evaluate the proposed technique, sinusoidal and sawtooth signals are applied as analog inputs to the proposed system. Adaptivity, speed, and accuracy are the main motivations of this work, which provide high accuracy compared to other techniques, up to 9.6 ENOB and 59.2 SNR with sawtooth signal and 9.5 ENOB and 59.2 SNR with sinewave signals.

Publisher

Hindawi Limited

Subject

Artificial Intelligence,Computer Networks and Communications,Computer Science Applications,Civil and Structural Engineering,Computational Mechanics

Reference22 articles.

1. A bit cycling method for improving the DNL/INL in successive approximation register (SAR) analog-to-digital converter (ADC);H. Fan

2. A non-linearity compensation technique for charge-redistribution sar adcs;E. Alvarez-Fontecilla

3. An ADC BIST using on-chip ramp generation and digital ORA

4. Error Correction Method of TIADC System Based on Parameter Estimation of Identification Model

5. A 16-Bit 120 MS/s Pipelined ADC Using a Multi-Level Dither Technique

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