A Histogram-Based Digital Background Calibration Technique for Pipelined A/D Converters
Author:
Affiliation:
1. Amirkabir University of Technology (Tehran Polytechnic),Integrated Circuits Design Laboratary,Electrical Engineering Depatment,Tehran,Iran
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10151848/10152300/10152348.pdf?arnumber=10152348
Reference22 articles.
1. A Low-Power Low-Cost On-Chip Digital Background Calibration for Pipelined ADCs
2. Statistics-Based Digital Background Calibration of Residue Amplifier Nonlinearity in Pipelined ADCs
3. A Square Wave-Based Digital Foreground Calibration Algorithm of a Pipeline ADC Using Approximate Harmonic Sampling
4. Non-Linear Calibration of Pipeline ADCs using a Histogram-Based Estimation of the Redundant INL
5. A 16b 120MS/s Pipelined ADC Using an Auxiliary-Capacitor Based Calibration Technique Achieving 90.5dB SFDR in 0.18 μm CMOS
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1. A new digital background calibration technique for pipeline analog to digital converters using decision points of the voltage transfer characteristics;Analog Integrated Circuits and Signal Processing;2023-11-22
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