An interstage gain calibration technique for pipelined ADCs exploiting complementary dithering and calibration windows detector-Reference-Cited by-同舟云学术

An interstage gain calibration technique for pipelined ADCs exploiting complementary dithering and calibration windows detector

Published:2024-04-25 Issue:8 Volume:21 Page:20240121-20240121
ISSN:1349-2543
Container-title:IEICE Electronics Express
language:en
Short-container-title:IEICE Electron. Express

Author:

Zhai Huaiyu¹²,Jia Hanbo¹,Guo Xuan¹,Jiang Zilin¹²,Zhang Yuzhen¹²,Wang Dandan¹²,Wu Jin¹²

Affiliation:

1. Institute of Microelectronics of the Chinese Academy of Sciences

2. University of Chinese Academy of Science

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Link

https://www.jstage.jst.go.jp/article/elex/21/8/21_21.20240121/_pdf

Reference31 articles.

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3. [3] A.M.A. Ali, et al.: “A 14bit 1GS/s RF sampling pipelined ADC with background calibration,” IEEE J. Solid-State Circuits 49 (2014) 2857 (DOI: 10.1109/JSSC.2014.2361339).

4. [4] J. Wu, et al.: “Dither-based background calibration of capacitor mismatch and gain error in pipelined noise shaping successive approximation register ADCs,” Electronics Letters 55 (2019) 984 (DOI: 10.1049/el.2019.0872).

5. [5] A.M.A. Ali, et al.: “A 14-bit 2.5GS/s and 5GS/s RF sampling ADC with background calibration and dither,” 2016 IEEE Symp. VLSI Circuits (2016) 1 (DOI: 10.1109/VLSIC.2016.7573537).