Time-Variant Modeling and Analysis of Multiplying Delay-Locked Loops

Author:

Santiccioli AlessioORCID,Samori Carlo,Lacaita Andrea L.ORCID,Levantino SalvatoreORCID

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Cited by 13 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Linear Periodically Time-Variant Digital PLL Phase Noise Modeling Using Conversion Matrices and Uncorrelated Upsampling;IEEE Transactions on Circuits and Systems I: Regular Papers;2024

2. Phase Noise Analysis for Stochastically Injected Oscillators;IEEE Transactions on Circuits and Systems II: Express Briefs;2023-08

3. A Sub-100 fs-Jitter 8.16-GHz Ring-Oscillator-Based Power-Gating Injection-Locked Clock Multiplier With the Multiplication Factor of 68;IEEE Journal of Solid-State Circuits;2023-01

4. Phase Noise Analysis of Periodically ON/OFF Switched Oscillators;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-01

5. Multirate Timestamp Modeling for Ultralow-Jitter Frequency Synthesis: A Tutorial;IEEE Transactions on Circuits and Systems II: Express Briefs;2022-07

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