Phase Noise Analysis of Periodically ON/OFF Switched Oscillators-Reference-Cited by-同舟云学术

Phase Noise Analysis of Periodically ON/OFF Switched Oscillators

Published:2023-01 Issue:1 Volume:70 Page:54-63
ISSN:1549-8328
Container-title:IEEE Transactions on Circuits and Systems I: Regular Papers
language:
Short-container-title:IEEE Trans. Circuits Syst. I

Author:

Castoro Giacomo¹^ORCID,Dartizio Simone M.¹^ORCID,Lacaita Andrea L.¹^ORCID,Levantino Salvatore¹^ORCID

Affiliation:

1. Dipartimento di Elettronica, Informazione e Bioingegneria, Politecnico di Milano, Milano, Italy

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture

Link

http://xplorestaging.ieee.org/ielx7/8919/10025563/09913207.pdf?arnumber=9913207

Reference32 articles.

1. General SSCR vs. cycle-to-cycle jitter relationship with application to the phase noise in PLL

2. Time-Variant Modeling and Analysis of Multiplying Delay-Locked Loops

3. A 97fsrms-jitter and 68-multiplication factor, 8.16 GHz ring-oscillator injection-locked clock multiplier with power-gating injection-locking and background multi-functional digital calibrator;park;IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers,2022

4. A Quadrature Pulse Generator for Short-Range UWB Vehicular Radar Applications Using a Pulsed Oscillator and a Variable Attenuator

Cited by 3 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Direct determination of instantaneous values of periodically switched circuits based on difference equations;Engineering Science and Technology, an International Journal;2024-03

2. Linear Periodically Time-Variant Digital PLL Phase Noise Modeling Using Conversion Matrices and Uncorrelated Upsampling;IEEE Transactions on Circuits and Systems I: Regular Papers;2024

3. A Sub-50-fs RMS Jitter, 103.5-GHz Fundamental-Sampling PLL With an Extended Loop Bandwidth;IEEE Solid-State Circuits Letters;2023